Why do the EMIF Efficiency Monitor counters “No readdatavalid Count” and “Master Write Idle Count” continue to incorrectly increment after traffic has completed? - Why do the EMIF Efficiency Monitor counters “No readdatavalid Count” and “Master Write Idle Count” continue to incorrectly increment after traffic has completed? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may see the EMIF Efficiency Monitor counters “No readdatavalid Count” and “Master Write Idle Count” continue to incorrectly increment after the Traffic Generator 1.0 (TG1) has completed sending traffic and subsequently resetting the Efficiency Monitor status registers by clicking on the Clear Status Registers button. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 14012341266 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']