Speed Change Issue for Arria V Hard IP for PCI Express IP Core - Speed Change Issue for Arria V Hard IP for PCI Express IP Core Description The Arria V Hard IP for PCI Express IP Core may enter the LTSSM state Recovery.Rcvlock after a speed change from Gen1 to Gen2 or from Gen2 to Gen1. Resolution This issue is fixed in version 13.1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']