Why do memory reads and writes fail to my PCI Express Endpoint enabled BAR locations? - Why do memory reads and writes fail to my PCI Express Endpoint enabled BAR locations? Description Memory read and write transaction may fail if the PCI Express® Device Identification Class Code Register is set to 0. A class code of 0 is reserved for devices built before class code definitions were finalized (pre PCI™ 2.0). Consequently, this is an invalid Device Class for PCI Express. Resolution You can obtain valid Device Class codes from the PCI-SIG® PCI Code and ID Assignment Specification . Related Articles Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']