Why do I observe an incorrect frequency from a cascaded IOPLL IP output in simulation? - Why do I observe an incorrect frequency from a cascaded IOPLL IP output in simulation? Description You may see an incorrect frequency or behavior during the simulation of cascaded IOPLL IP for Intel® Arria® 10, Intel Cyclone® 10 GX, and Intel® Stratix® 10 devices. This is due to a bug in the simple simulation model generated from the IOPLL IP by default. Resolution To work around this, enable the PLL Auto Reset option in Physical PLL Settings before IOPLL IP generation. This enables the advanced simulation model, which is not impacted by this issue. This problem was fixed in Intel® Quartus® Prime Software version 22.1 Custom Fields values: ['novalue'] Troubleshooting 1807398508 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 18.1.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']