Why does the Viterbi Megacore generate an incorrect rr bus width? - Why does the Viterbi Megacore generate an incorrect rr bus width? Description Due to a problem in the Viterbi Megacore® version 16.0 and earlier, the rr bus width calculation is always equal to n*softbit, therefore the rr bus width is incorrect when you select TCM mode. Resolution To workaround this issue: 1. Open the altera_vit_ii_parameters.tcl file from the following directory <Installation path>\ip\altera\dsp\altera_vit_ii\src\tcl_libs 2. Comment out line 414, and then add the following script if { == "T" } { set_parameter_value rr_size [expr **2] } else { set_parameter_value rr_size [expr *] } 3. Re-open Quartus® and Re-generate the MegaCore This problem is scheduled to be fixed in a future release of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 386772; False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']