Why does the rx_digitalreset and tx_digitalreset signals of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core cannot connect to the Transceiver PHY reset controller Intel® FPGA IP in the Platform Designer? - Why does the rx_digitalreset and tx_digitalreset signals of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core cannot connect to the Transceiver PHY reset controller Intel® FPGA IP in the Platform Designer? Description Due to a problem with the Intel® Quartus® Prime Software, the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP has incorrect type of interface for the rx_digitalreset and tx_digitalreset signals, therefore you cannot connect these two signals to the Transceiver PHY reset controller Intel FPGA IP in the Platform Designer. The correct type of interface for the rx_digitalreset and tx_digitalreset signals are conduit NOT reset. Resolution Export the rx_digitalreset and tx_digitalreset signals from the Platfrom Designer and manually connect at register transfer level (RTL). This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 537354; False ['1G 2.5G 5G 10G Multi-rate Ethernet PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Arria® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']