Is there a problem if a floating voltage exists on VCC_AUX before it is ramped in Arria V, Cyclone V, Stratix IV, and Stratix V devices? - Is there a problem if a floating voltage exists on VCC_AUX before it is ramped in Arria V, Cyclone V, Stratix IV, and Stratix V devices? Description No, there is no problem if a floating voltage exists on VCC_AUX before it is ramped in Arria® V, Cyclone® V, Stratix® IV, and Stratix V devices. Leakage can occur between VCC and VCC_AUX when VCC_AUX is ramped after VCC. This is an expected behavior in these device families. The leakage occurs through the passgate transistors causing VCC_AUX to float to approximately 0.6V prior to the power supply ramping up. 0.6V is below the power on reset (POR) trip point. This will cause no functional failure or any reliability concern to the device. This can only be observed if VCC is powered up before VCC_AUX and the regulators were designed to leave the power supplies to float before they ramp up. Related Articles Is there any problem if a floating voltage exists on VCCH_GXB before it is ramped in Arria II, Arria V, Stratix IV, and Stratix V devices? Why is a floating voltage observed on the 2.5V VCCIO rail during power-up of Cyclone IV GX, Cyclone V, Arria V, Stratix IV or Stratix V devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']