Are there any known problems with rxvalid occasionally deasserting when the Rate Match FIFO performs a SKP insert operation when using Gen3 soft PIPE on Stratix® V GX devices? - Are there any known problems with rxvalid occasionally deasserting when the Rate Match FIFO performs a SKP insert operation when using Gen3 soft PIPE on Stratix® V GX devices? Description Yes, there is a known problem in PCI Express Gen3 soft PIPE where rxvalid is occasionally de-asserted when the Rate Match FIFO performs an SKP insertion on Stratix® V GX devices. This issue is seen in systems that do not use a common reference clock. No issues are seen when a common clock is used. Resolution To workaround this issue, ignore the rxvalid signal during SKP insertion and instead use rxstatus on the PIPE interface to know when an SKP character is inserted (rxstatus = 001). Custom Fields values: ['novalue'] Troubleshooting 1408110822 False ['PHY for PCI Express (PIPE) IP'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Stratix® V FPGAs', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']