Altera® Agilex™ FPGAs Network-on-Chip (NoC): Implementation & Optimization - Same course in Japanese: コース名: アルテラ® Agilex™ FPGA ネットワーク・オン・チップ (NoC) の概要と実装パート2 53 Minutes This training is part 2 of 2. Altera® Agilex™ 7 M-Series FPGAs introduce a hardened, but customizable, Network-on-Chip interconnect, or NoC, at the top and bottom I/O periphery of the device. Including the NoC in a design that uses an external memory interface (EMIF) or on-chip high bandwidth memory (HBM2E) reduces FPGA fabric congestion at the I/O and makes it possible to saturate memory bandwidth, even while running FPGA logic at a slower speed, making it much easier to close timing. This second part of the training describes the design flow in the Altera® Quartus® Prime software for implementing a NoC design. It also highlights how to get the best performance out of a NoC design through device resource planning and other optimization recommendations. Course Objectives At course completion, you will be able to: Implement a NoC design using IP and tools found in the Altera® Quartus Prime software Plan device resource usage for a NoC design Optimize a NoC implementation Skills Required Background in digital logic design Knowledge of EMIF and/or HBM2E implementation in Altera® Agilex™ FPGA devices Familiarity with the Altera® Quartus® Prime software and, optionally, its features, including Platform Designer and Interface Planner If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ONOCIMPL. FPGA_ONOCIMPL. <p>Altera Agilex FPGAs Network-on-Chip (NoC): Implementation & Optimization</p>