Why I see Timing Violation If audio_clk Is Not Driven At Same Clock Source As ls_clk? - Why I see Timing Violation If audio_clk Is Not Driven At Same Clock Source As ls_clk?
Description You will observe timing violation in the TX core if you are not driving the audio_clk with the same clock source as ls_clk. This is due to audio_info_ai[48] and audio_info_ai[47:0] are not synchronized to the same clock domain internally. Resolution You can perform clock domain synchronization for audio_info_ai[48] to ls_clk externally if you are driving audio_clk with different clock source as ls_clk.
Custom Fields values:
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Troubleshooting
FB: 475331;
True
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['FPGA Dev Tools Quartus® Prime Software Pro']
17.1
15.1
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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