Why does the E-tile CPRI PHY Intel® FPGA IP have an unconstrained clock *|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out? - Why does the E-tile CPRI PHY Intel® FPGA IP have an unconstrained clock *|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 or earlier, there is an unconstrained clock in the E-tile CPRI PHY Intel® FPGA IP as follows: *|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out Resolution This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 15013356673 False ['E-Tile CPRI PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ FPGA Portfolio', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']