Why does Agilex® 7 FPGA M-Series fail to be reconfigured after applying a software cold reset from U-Boot proper in Quartus® Prime Pro release 26.1? - Why does Agilex® 7 FPGA M-Series fail to be reconfigured after applying a software cold reset from U-Boot proper in Quartus® Prime Pro release 26.1? Description Due to an incorrect implementation of the cold reset flow in U-Boot proper, in Agilex® 7 FPGA M-Series in release 26.1, the FPGA/JTAG is not kept in a clean idle state, resulting in the JTAG reconfiguration rejection. This causes the following error observed when you try to reconfigure the device after the cold reset: SOCFPGA_AGILEX7M # reset resetting ... Mailbox: Issuing mailbox cmd REBOOT_HPS rolando@rolando3-linux-lab:~/tasks/testbin$ quartus_pgm -c 1 -m jtag -o "p;ghrd.hps.rbf@2" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 26.1.0 Build 110 03/26/2026 SC Pro Edition Info: Copyright (C) 2026 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Tue Jun 30 18:42:30 2026 Info: System process ID: 93542 Info: Command: quartus_pgm -c 1 -m jtag -o p;ghrd.hps.rbf@2 Info (213046): Using programming cable "Intel Agilex M-Series Development Kit - HBM2e Edition on AN04WVAW035PS.an.altera.com [1-12]" Info (213011): Using programming file ghrd.hps.rbf with checksum 0xA66FE7E5 for device AGMF039R47AC@2 Info (209060): Started Programmer operation at Tue Jun 30 18:42:32 2026 Info (18942): Configuring device index 2 Error (18952): Error status: Device does not accept configuration request Error (18939): Unexpected error in JTAG server: JTAG chain broken Error (18952): Error status: Detected error when rescan jtag chain Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue Jun 30 18:42:43 2026 Error: Quartus Prime Programmer was unsuccessful. 4 errors, 0 warnings Error: Peak virtual memory: 1235 megabytes Error: Processing ended: Tue Jun 30 18:42:43 2026 Error: Elapsed time: 00:00:13 Error: System process ID: 93542 Resolution To work around this problem, you can disable the watchdog timer before issuing the cold reset. This can be done using the wdt stop command from the U-Boot shell as shown next: SOCFPGA_AGILEX7M # wdt list watchdog@ffd00200 (designware_wdt) SOCFPGA_AGILEX7M # wdt dev watchdog@ffd00200 SOCFPGA_AGILEX7M # wdt stop SOCFPGA_AGILEX7M # reset Note: You need to build your U-Boot to support the wdt command by setting CONFIG_CMD_WDT=y in your build configuration. You can also apply the cold reset from Linux, in which the error is not observed. For this, you can use the reboot command from the Linux shell. This problem will be fixed in a future release. Custom Fields values: Troubleshooting ES-14578 novalue ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex® 7 FPGA M-Series']