Why do the Intel® Arria® 10 10GBASE-R Design Example User Guide and simulation test bench file show an incorrect Tx/Rx SC FIFO offset address ? - Why do the Intel® Arria® 10 10GBASE-R Design Example User Guide and simulation test bench file show an incorrect Tx/Rx SC FIFO offset address ? Description Due to a problem with the Intel® Arria® 10 10GBASE-R design example, the register map offset address for RX SC FIFO is 9400h and TX SC FIFO is 9600h. However, in the "Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide" (ug-20016), the offset address for RX SC FIFO is D400h and TX SC FIFO is D600h. Resolution The 10GBASE-R design example's register map offset address for TX SC FIFO and RX SC FIFO will be amended to match with register map offset address in the ug-20016 design example user guide. This problem will be fixed in a future version of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 557754; False ['10GBASE-R PHY IP', '1G 10GbE and 10GBASE-KR PHY Arria® 10 FPGA IP', '1G 2.5G 5G 10G Multi-rate Ethernet PHY IP', 'Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']