Why the reported PFD frequency in the PLL Usage Summary is over the specification stated in the device data sheet? - Why the reported PFD frequency in the PLL Usage Summary is over the specification stated in the device data sheet? Description The input frequency (Fref) to the PLL Phase Frequency Detector (PFD) is FREF = FIN / N. Depending on the fitter selected phase-locked loop (PLL) parameters, the settings might not be optimized and causing the reported FREF to PLL PFD to be over the maximum frequency value reported in the device data sheet. This affects PLLs in integer mode. This occurs in the Quartus® II software version 12.0 and earlier. Resolution If your calculated FREF is over the maximum frequency specified in the device datasheet, you can use fractional PLL mode until this is fixed in a future version of the Quartus II software. This problem will be fix in future version of the Quartus II software. Related Articles Why does the PLL Usage Summary report minimum and maximum lock values that are outside of my input clock frequency? Custom Fields values: ['novalue'] Troubleshooting 53768 False ['Generic Component'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1.2 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']