Why does my VIP Suite design in Qsys have timing errors between the frame buffer and the DDR memory? - Why does my VIP Suite design in Qsys have timing errors between the frame buffer and the DDR memory? Description This is a problem when Qsys generates the Frame Buffer and De-Interlacer core. The SDC files are not automatically added to the Qsys system design folder. Resolution To workaround this problem you can manually add the SDC file for the Frame Buffer of De-Interlacer core by going to the <quartus_installation_path>\ip\altera\<name_of_ip>, copying the .sdc file from this folder and adding this file to your project folder. You will then need to add this SDC file to the list of SDC files that the TimeQuest Timing Analyzer evaluates when running timing analysis in your design. This is done through the Assignments > Settings > TimeQuest Timing Analyzer settings. This will be fixed in a future release of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']