When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are the o_clk_rec_div66 and o_clk_pll_div66 clock rates reported incorrectly during timing analysis? - When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are the o_clk_rec_div66 and o_clk_pll_div66 clock rates reported incorrectly during timing analysis? Description Due to a problem with Intel® Quartus® Prime software Pro version 18.0.1 and earlier, the output clock frequency of the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, signals o_clk_rec_div66 and o_clk_pll_div66 is reported incorrectly in timing analysis. The correct frequency for o_clk_rec_div66 is 156.25MHz and o_clk_pll_div66 is 390.625MHz. Resolution No workaround for this problem is available. This problem has been fixed starting in Intel® Quartus® Prime Pro software version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 587832; True ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']