Agilex 3 AVST programming fails - Agilex 3 AVST programming fails Hi, We are trying to program an Agilex 3 device over the AVST8 interface, implemented through a CPU using SPI and bit-banging. Setup (see picture below): Data is shifted into a serial-to-parallel converter via SPI. AVST_CLK is generated from the SPI CS signal. AVST_VALID and AVST_READY are controlled by GPIOs. With this setup, we can mimic the passive serial programming approach used on Arria FPGAs. What works: Programming and testing over JTAG works fine. The FPGA design itself runs correctly. What does not work: During AVST8 programming, AVST_READY goes low after ~8210 bytes and never returns high. Programming sequence we follow: CPU initializes pins: nCONFIG=0, AVST_VALID=0 CPU sets nCONFIG=1 FPGA pulls nSTATUS=0 CPU sets nCONFIG=0 FPGA sets nSTATUS=1 CPU provides some clock cycles (~81 cycles) on AVST_CLK (since AVST_READY is low) FPGA sets AVST_READY=1 CPU sets AVST_VALID=1 and streams configuration data After 8210 cycles, FPGA sets AVST_READY=0 CPU sets AVST_VALID=0 and continues clocking At this point, AVST_READY never goes high again. What we observed: If we deliberately corrupt the configuration data, nSTATUS goes low after a few cycles — as expected. This suggests that the FPGA is checking data integrity, but something prevents AVST_READY from recovering. Our bit-banged AVST_CLK frequency is only about 60 kHz. Could this low frequency be the root cause? Question: Why does AVST_READY stay low after 8210 bytes? Is the slow clock (60 kHz) causing the issue, or are we missing something in the programming sequence? Thanks in advance for your support! Replies: Re: Agilex 3 AVST programming fails We're glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: Agilex 3 AVST programming fails Hi, I noticed that the nStatus drops to a low value for a short time, which indicates that something is wrong with the data. I fixed the problem and the programming is working. Best regards, Samuel Replies: Re: Agilex 3 AVST programming fails Hi Farabi, >60kHz is too slow Is there a time out or something? Unfortunately, we cannot increase the speed without further effort. We first need to implement a Linux driver to optimize access to the SPI interface and the pins. I will get back to you in a few weeks. If you have any further ideas, please let me know. Best regards, Samuel Replies: Re: Agilex 3 AVST programming fails Hi Alan, we use custom logic. Best regards, Samuel Replies: Re: Agilex 3 AVST programming fails Hello, Can you try higher frequency for AVST_CLK? 60kHz is too slow. Can start from 1MHz. You can also keep AVST_VALID -> high during streaming, even after AVST_READY goes low. Only send the idle clock cycles after AVST_READY goes low, with AVST_VALID = 0. Please check signal condition with oscilloscope, is it clean or too noisy. regards, Farabi Replies: Re: Agilex 3 AVST programming fails Hi, May I know are you using PFL IP or custom logic for AVST config? Thanks, Best regards, Alan