Timing-Related Warning Messages for DDR2 and DDR3 SDRAM Controller with UniPHY When Sharing PLLs on Stratix V Devices - Timing-Related Warning Messages for DDR2 and DDR3 SDRAM Controller with UniPHY When Sharing PLLs on Stratix V Devices Description When instantiating a design in PLL/DLL slave mode on a Stratix V device, the TimeQuest Timing Analyzer may display warning messages similar to the following: Warning: Ignored filter at slave_report_timing_core.tcl(176): slave_inst0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads| dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin could not be matched with a keeper or register or port or pin or cell or net Warning: Command get_path failed Resolution This issue has no workaround. The warning messages can be safely ignored; however, do not rely on the accuracy of the resulting timing analysis. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']