Error: intel_jesd204c_f_0: Error when executing: quartus_tlg --verbose <local path>/0001_intel_jesd204c_f_0_gen/simulation/models/jesd204c_f_ed - Error: intel_jesd204c_f_0: Error when executing: quartus_tlg --verbose <local path>/0001_intel_jesd204c_f_0_gen/simulation/models/jesd204c_f_ed Description Due to a problem in the Quartus® Prime Pro Edition Software v21.4 in Windows* OS, this error will appear when generating the example design of F-Tile JESD204C FPGA IP. This error is caused by the length of the file paths supported by the OS. Resolution There are two solutions to solve this problem: On Windows* OS settings, change the path of the environment variables (User variables for Administrator) TEMP and TMP into shorter path e.g. From: TEMP C:\Users\MyUserName\AppData\Local\Temp TMP C:\Users\MyUserName\AppData\Local\Temp To: TEMP C:\Temp TMP C:\Temp Change Windows* OS settings to support longer File Paths. Search for regedit in Windows Start and open it . Navigate to the following path: Computer\HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem Find LongPathsEnabled and double-click it . Change the Value Data from 0 to 1 , click OK. Restart the PC and generate the example design . Custom Fields values: ['novalue'] Troubleshooting 14016482442 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.4 ['HardCopy™ ASIC Devices', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']