HDMI Designs Lock HDMI RX Core but No Display from HDMI TX - HDMI Designs Lock HDMI RX Core but No Display from HDMI TX Description When you run the HDMI designs for Arria 10, Arria V, and Stratix devices, the HDMI RX core locks but nothing is displayed from the HDMI TX core. This issue may be caused by the Chip Planner\'s placement of the generic PLL ( pll_hdmi_tx ). If pll_hdmi_tx is placed further away from the transceiver PLL, the clock jitter may affect the HDMI TX core. Resolution Place pll_hdmi_tx next to the transceiver PLL . This issue will be fixed in a future version of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']