How can I enable timing analysis of the HPS Ethernet interfaces via the FPGA? - How can I enable timing analysis of the HPS Ethernet interfaces via the FPGA? Description Timing analysis of the HPS Ethernet interfaces via the FPGA is disabled by default. It can be enabled on Cyclone® V SoC and Arria® V SoC by following the steps in the Resolution section. Resolution To enable timing analysis in the Quartus® Prime Standard Edition Software for HPS Ethernet interfaces via the FPGA, add the following global assignment in the Quartus Settings File (.qsf) for your project: set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING ON Notes: You must ensure that the external interfaces on the FPGA are constrained For details on constraining RGMI Iinterfaces, see the Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature web page. This global assignment replaces the quartus.ini variable used in the RGMII and SGMII examples on Rocketboards.org From the Quartus II software version 15.1, the Platform Designer will add constraints for the HPS EMAC to FPGA fabric interface. This information is scheduled to be included in a future release of the Cyclone V SoC and Arria V SoC Technical Reference Manuals. Custom Fields values: ['novalue'] Troubleshooting FB: 251488 490143 391699; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']