Some Cyclone III RapidIO Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer - Some Cyclone III RapidIO Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer Description RapidIO x1 variations at data rate 3.125 Gbaud that target a Cyclone III device compile with a critical warning from the TimeQuest timing analyzer indicating that timing requirements are not met and worst-case hold slack is negative. Because these variations do not meet timing requirements using the default place and route settings, a design that contains one of these variations does not operate properly. Resolution Turn on the fitter setting Perform Clocking Topology Analysis During Routing before compiling your RapidIO design. This issue is fixed in version 10.1 of the RapidIO MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.1 10.0 ['Cyclone® FPGAs', 'Cyclone® III FPGAs'] ['novalue'] ['novalue'] ['novalue']