Internal Error: Sub-system: LVDS, File: /quartus/periph/lvds/lvds_gen5_av.cpp, Line: 3237 - Internal Error: Sub-system: LVDS, File: /quartus/periph/lvds/lvds_gen5_av.cpp, Line: 3237 Description Due to a problem in the Quartus® II software version 12.1 and later, you may see this internal error when you have an LVDS interface configured in soft-CDR mode and the parallel data is registered by an unrelated clock rather than the recovered clock. This error affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices. Resolution To work around this issue, register the parallel data from the LVDS interface with the recovered clock. This configuration is scheduled to give an error message in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']