Why does my F-Tile PMA/FEC Direct PHY Intel® FPGA IP design fail to compile in the Support-Logic Generation stage when the design has at least one multiple PMA lanes variant with “Datapath clocking mode” set to “PMA” ? - Why does my F-Tile PMA/FEC Direct PHY Intel® FPGA IP design fail to compile in the Support-Logic Generation stage when the design has at least one multiple PMA lanes variant with “Datapath clocking mode” set to “PMA” ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3, when the design has at least one multiple PMA lanes variant with “Datapath clocking mode” set to “PMA”, it will fail to compile in the Support-Logic Generation stage with “Error (21842): Solver failed to find a solution” message. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.1. To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 or earlier, replace your multiple PMA lanes variant with multiple instances of a 1-channel variant. Custom Fields values: ['novalue'] Troubleshooting 18017924552 False ['Transceiver PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']