Why does the 25G Ethernet Intel® FPGA IP fail to achieve 100% throughput? - Why does the 25G Ethernet Intel® FPGA IP fail to achieve 100% throughput? Description Due to a problem in the 25G Ethernet Intel® FPGA IP core, for Intel® Quartus® Prime Pro Edition Software version 20.2 and earlier, you may see the IP fail to achieve 100% throughput. This is because the IP does not compensate for the data rate loss due to RSFEC Alignment Marker Insertion on the TX data path. The 25G Ethernet Intel® FPGA IP Core is not adhering to section 108.5.2.2 "rate compensation for codeword markers in the transmit direction" of the IEEE 802.3 spec. As a result, the IP is unable to achieve throughput higher than 99.995%. Resolution No workaround to this problem exists. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3 for the Intel® Stratix® 10 device. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4 for the Intel® Arria® 10 device. Custom Fields values: ['novalue'] Troubleshooting 1508187436 False ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 20.3 19.3 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']