Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) - Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) We are using a Stratix 10 L-Tile/H-Tile Transceiver Native PHY to implement a DisplayPort TX and RX. The transceiver is set as Basic (Enhanced PCS), TX/RX Duplex. The TX PMA is set as Non bonded, with 2 TX PLL clock inputs. One of the TX PLL clock inputs is driven by a fPLL and used for rates from 1.62G up to 13.5G. The other clock input is driven by two ATX PLLs (one working as Main PLL, the other as GXT Clock Buffer) and used for 20G rate. This works ok. The problem is that DisplayPort requires controlled skew between the 4 TX channels. That is, we need bonding for the 4 TX channels. If we set the TX PMA as "PMA only bonding" it seems we cannot have anymore multiple TX PLL clock inputs but just a single one. How can we use the Stratix 10 PHY to implement DisplayPort TX rates from 1.62G up to 20G with 4 bonded channels (= 4 lanes)? Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP. Please let me know if you have any questions or concerns. Thank you. Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, Thank you for your question. From your description, you are asking about the maximum data rate supported by the Stratix 10 ATX PLL when operating in bonded mode. You are correct — according to AN 778: Intel® Stratix® 10 L‑Tile/H‑Tile Transceiver Usage , channel bonding is not supported for data rates above 17.4 Gbps . We understand this may be inconvenient, and we appreciate your patience. In parallel, I am consulting with our DisplayPort IP experts to confirm whether the DP IP can support 20 Gbps while using bonded channels. I will update you as soon as I receive a definitive response. If you do not hear back from me by the end of next week, please feel free to ping me. Thank you. Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible. Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, It looks like bonding is not supported at rates > 17.4G: Also the ATX PLL refuses to configure for 20G with bonding: Can you please help? Regards Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Yes, you understood it right. As 20G can be achieved only by GXT channels and for the clocking at that speed ATX pll is the preferred choice. Refer section 3.1 PLLs of the same document. Regards Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, We need to generate TX link rates spanning from 1.62G to 20G. Are you saying that we can get rid of the fPLL and use only one single ATX PLL with bonding and driving all 4 GXT channels? Regards Replies: Re: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX) Hi, Please follow the guideline in the L- and H-Tile Transceiver PHY User Guide: https://docs.altera.com/r/docs/683621/current/l-and-h-tile-transceiver-phy-user-guide/pma-bonding As I understand you need PMA only bonding of the channels. For this, you will need only one ATX pll clock to be driving all the channels. Another important consideration you have to make, is the channel placements. As you need max 20G, you will need to use the GXT channels. Hope this helps. Regards