Why does the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP Design Example generation fail? - Why does the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP Design Example generation fail? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, generation of the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP design example can fail even when using the default configuration. Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 15013541796 False ['L-Tile H-Tile Transceiver Native PHY Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']