Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v - Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v Description Due to a problem in the Intel® Arria® 10 Hard IP for PCI Express*, you will see the following warnings during analysis and elaboration when using the Intel® Quartus® II or Intel® Quartus® Prime Standard software. Warning (10240): Verilog HDL Always Construct warning at altpciexpav128_txresp_cntrl.v(344): inferring latch(es) for variable "payload_limit_cntr", which holds its previous value in one or more paths through the always construct Info (10041): Inferred latch for "payload_limit_cntr[0]" at altpciexpav128_txresp_cntrl.v(344) Info (10041): Inferred latch for "payload_limit_cntr[1]" at altpciexpav128_txresp_cntrl.v(344) Info (10041): Inferred latch for "payload_limit_cntr[2]" at altpciexpav128_txresp_cntrl.v(344) Info (10041): Inferred latch for "payload_limit_cntr[3]" at altpciexpav128_txresp_cntrl.v(344) Resolution These warning can be safely ignored, and have been fixed in Intel® Quartus® Prime Pro software starting in version 16.1. Custom Fields values: ['novalue'] Troubleshooting FB: 309656; False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Standard', 'FPGA Dev Tools Quartus II Software'] 16.1 15.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']