PCIe Gen5/6 Switch (FPGA IP for Altera Devices) - Mobiveil’s PCIe Gen5 Switch FPGA IP enables multi-port connectivity with support for bifurcation, NTB, and port arbitration. It is tailored for high-speed switching in data centers, HPC, and next-gen… Mobiveil, Inc.(a GlobalLogic company) is a fast-growing technology company headquartered in Santa Clara, California, specializing in Silicon Intellectual Properties (SIP), application platforms, and… Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series FPGA PCIe® multi-port switch IP built with x16 upstream / up to x8 per downstream, non-blocking fabric, cut-through & store-and-forward modes, and full PCIe 5.0 compliance (backward-compatible to Gen4/3/2/1). Solution stitches the FPGA’s PCIe HIPs (upstream + multiple downstream ports) with a Mobiveil switch fabric to create a configurable transparent/non-transparent PCIe switch. Supports single-port & multi-port configs, flexible upstream/downstream lane widths, 32/64/128/256/512-bit datapaths, flow control in both directions, advanced error reporting, power management (L0s/L1/L1 sub-states), and per-port feature sets. Includes AMBA master/slave option for app logic, parallel address decoding at each ingress, arbitration (round-robin / strict-priority with starvation detection), and full collateral (RTL, UVM TB, protocol checkers, perf monitors, synth guides). Built to PCIe 5.0 (32 GT/s); roadmap aligns with Gen6 controller/switch trends. ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Industrial Transportation Wireless PCIe Gen5/6 Switch (FPGA IP for Altera Devices) Key Features Upstream up to x16 lanes, downstream up to x8 lanes, with programmable link widths and reconfiguration support. Offering Brief No No No No Encrypted Verilog Verilog Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Yes Agilex™ 7 FPGA Starter Kit Yes 24.3.1 Offering Brief Production a1JUi000009TXWTMA4 What's Included RTL Code Ordering Information NA Direct a1JUi000009TXWTMA4 Production Intellectual Property (IP) a1MUi00000BO8shMAD a1MUi00000BO8shMAD Select 2026-07-01T15:29:45.000+0000 Mobiveil’s PCIe Gen5 Switch FPGA IP enables multi-port connectivity with support for bifurcation, NTB, and port arbitration. It is tailored for high-speed switching in data centers, HPC, and next-gen compute systems. The solution emphasizes low latency, scalable bandwidth, and flexible integration for Altera platforms. Partner Solutions