Are there any known errors in the Stratix EP1S80 DSP Development Board data sheet? - Are there any known errors in the Stratix EP1S80 DSP Development Board data sheet? Description Notes (1) and (2) for Table 29 are incorrect. Below are the corrections to these notes: (1) Pin 1 is tied to GND. Pins 2, and 3 are no connects. (2) Pin 1 is tied to 5-V. Pins 5, and 7 are tied to 3.3-V. Pins 3, 15, 17, and 19 are no connects. Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 are tied to ground. In Figure 8, Pin 6 of JP24 is not connected to pin D31 on the chip. It is connected to pin D30. Custom Fields values: ['novalue'] Troubleshooting novalue False ['DSP'] ['novalue'] novalue novalue ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']