What is the maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core? - What is the maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core?
Description The maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core is 250 MHz. Please note that the actual allowable maximum frequency depends on user design.
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Troubleshooting
1507098925
False
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['FPGA Dev Tools Quartus® Prime Software Pro']
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['Stratix® 10 FPGAs and SoCs']
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['novalue']
['novalue'] - 2021-08-25
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