Ethernet RGMII Cyclone V - Ethernet RGMII Cyclone V Hi, I'm trying to implement an ethernet application in RGMII mode with a NIOS processor in a Cyclone V 5CSEMA5F31 FPGA and Quartus Prime standard Edition 18.1. I followed a tutorial for Triple-Speed_Ethernet IP and I instantiated the following components in QSYS: - NIOS II Processor - CLOCK NIOS - On-Chip Memory (NIOS - TSE) - Triple-Speed Ethernet Intel FPGA IP (RGMII) - Scatter-Gather DMA Controller RX - Scatter-Gather DMA Controller TX - On-Chip Memory Intel FPGA IP (descriptor memory for sgdma) I created the Soc_system with the QSYS and I connected input and output to the respective ports. This error occurred during the Analysis&Synthesis : Error (15871): Input port DATAIN of DDIO_IN primitive "soc_system:comp_SoC_System|soc_system_eth_tse_0:eth_tse_0|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive I tried to use an ALTIOBUF component for the input bus RGMII_RX(3 downto 0) but it does not work. Can you help me? Thanks Bryan Replies: Re: Ethernet RGMII Cyclone V The solution is to use the Modular Scatter Gather DMA instead of the SGDMA that is obsolete. Replies: Re: Ethernet RGMII Cyclone V I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: Ethernet RGMII Cyclone V You can find it in c:\intelFPGA\20.1\ip\altera\altera_gmii_to_rgmii_adapter. Replies: Re: Ethernet RGMII Cyclone V Hi Eric, thanks for the reply. Can you give me an example project or tutorial on this GMII/MII to RGMII adapter? Thanks, Bryan Idrobo Replies: Re: Ethernet RGMII Cyclone V The FPGA supports GMII/MII interface. For RGMII, you will need to add adaptor between GMII/MII to RGMII in FPGA fabric. Replies: Re: Ethernet RGMII Cyclone V Hi, Yes, the signal input "eth_tse_0_mac_rgmii_connection_rgmii_in" of the HPS is connected directly to the input ports of the top_level. I saw the project from Rocketboards but the 2 ethernet peripherals are connected to the HPS. Instead I need 1 ethernet peripheral to be controlled by NIOS processor in RGMII configuration. Thanks, Bryan Replies: Re: Ethernet RGMII Cyclone V Are your DATAIN directly connected to input pins? Alternatively, you may refer to below from Rocketboards. https://rocketboards.org/foswiki/Projects/CycloneVRGMIIExampleDesign