Why does the o_rx_pcs_ready signal fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet FPGA Hard IP? - Why does the o_rx_pcs_ready signal fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet FPGA Hard IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the o_rx_pcs_ready signal will fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet FPGA Hard IP when the variant is using both a 312.5MHz PMA reference clock and the Quartus Setting File(QSF) assignment VSR_MODE_LOW_LOSS is being used. Resolution To work around this problem, disable the QSF assignment VSR_MODE_LOW_LOSS. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16019784620 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']