Are there any known issues with the Altera PLL Reconfig IP for Arria 10, Stratix V, Arria V or Cyclone V devices which may cause reconfiguration to occasionally fail? - Are there any known issues with the Altera PLL Reconfig IP for Arria 10, Stratix V, Arria V or Cyclone V devices which may cause reconfiguration to occasionally fail? Description Yes there is an issue with the Altera® PLL Reconfig IP for Arria® 10, Stratix® V, Arria V and Cyclone® V devices in Quartus® Prime software versions prior to 16.1, In this IP there is a lack of synchronization of the locked signal, which is an asynchronous signal sourced from the PLL that is being reconfigured. This runs the small risk of causing a malfunction of the reconfiguration control state machine that the locked signal feeds, which operates in the mgmt_clk domain. This may result in a reconfiguration request to fail. Resolution This issue is fixed in Quartus Prime software version 16.1. Custom Fields values: ['novalue'] Troubleshooting FB: 199061; False ['PLL Reconfig IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.1 novalue ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']