Why am I seeing the CRC_ERROR signal pulled high during FPGA configuration? - Why am I seeing the CRC_ERROR signal pulled high during FPGA configuration? Description During the configuration process, the CRC_ERROR pin is a regular I/O pin until the FPGA enters user mode and then will start to function as the CRC_ERROR pin (if this function is enabled). Even though the I/O pins are tri-stated during the configuration process, this I/O (CRC_ERROR) pin buffer is turned off and is connected to an external 10k ohm pull-up, this will cause the I/O (CRC_ERROR) pin to be pulled high. When the FPGA enters user mode, the I/O (CRC_ERROR) pin buffer is turned on and will function as the CRC_ERROR pin where it will stay low until an error is detected. Resolution When monitoring the configuration process it is recommended to observe the optional INIT_DONE signal status as this will indicate if the FPGA has entered user mode. The low-to-high transition on INIT_DONE indicates the device has completed initialization and entered user mode. You will see INIT_DONE go high when the CRC_ERROR pin goes low. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']