Why does the Altera PLL fail to lock in simulation after installing the dp5 patch? - Why does the Altera PLL fail to lock in simulation after installing the dp5 patch? Description The Altera® PLL simulation model may fail to operate correctly and fail to assert the locked signal after installing the dp5 patch for version 13.0sp1 of the Quartus® II software. You will see this problem if you are simulating a PLL using Dynamic Phase Stepping or Dynamic Reconfiguration. The problem is with the simulation model, so does not affect the operation of the PLL when implemented in hardware. Resolution This problem is resolved in version 13.1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']