Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? - Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? Hello, I have a question regarding the unused CLK and PLL pins. Can they be left floating, or must they all be connected to GND? I reviewed the documentation again, and it suggests either grounding or connecting to VCCIO. What issues might arise if they are left floating? Could you please help me check my schematic, focusing only on the MAX10 FPGA part, to confirm if there are any other issues (including CLK and PLL pins)? Thank you very much. Replies: Re: Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? Hello Sir, I wish to follow up with you, do you have any more concerns on this issue? Or do you need more support/help before I close this thread? Regards, Aqid Replies: Re: Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? Hello, You can refer to each pin's requirement for unconnected ones in the pin connection guideline for MAX 10. If it mentions that you need to connect to VCCIO or GND, it means you can't leave it floating. There was no guaranteed behavior or effect on the device if you were not following the guidelines. Refer link below for the MAX10 PCG: https://www.intel.com/content/www/us/en/docs/programmable/683232/current.html?wapkw=max%2010%20pin%20connection%20guideline Regards, Aqid Replies: Re: Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? Hello, if you are unable to assist me with verifying the SCHEMATIC, please let me know. Additionally, could you please advise me on whether the unused CLK and PLL pins must be connected to GND? Currently, my PCB LAYOUT is relatively fixed, so I have directly connected these pins to GND, that's easy. Are there any other unused pins that require special treatment and cannot be left floating? Thanks ! Replies: Re: Regarding the 10M02SCM153, how should the unused pins, especially CLK and PLL, be handled? Could intel FAE help me to confirm this probram? whether it is true that unused clk and pll pins cannot be left floating? If so, I must modify the layout as soon as possible. As the issue has not been confirmed yet, we cannot proceed with the PCB fabrication. Thanks for your help.