How do I connect Intel® FPGA DDR4 PHY-Only IP with the DFI compliant Custom DDR4 Controller? - How do I connect Intel® FPGA DDR4 PHY-Only IP with the DFI compliant Custom DDR4 Controller? Description The DFI-compliant custom DDR4 Controller IP doesn’t have the same IO pins as Intel® FPGA DDR4 Controller IP. Please follow the solution to implement the DDR4 EMIF interface with the DFI-compliant custom DDR4 controller IP and Intel® FPGA DDR4 PHY-Only IP. Resolution The RAS/CAS/WE signals are multiplexed with address signals A[16:14] using the ACT signal per DDR4 protocol. The AFI bus provides raw access to these pins. The customer needs to use some small adaptation logic: map the AFI signals corresponding to A[16:14] to the DFI_ADDRESS signals for A[16:14] when ACT_N is low and to RAS/CAS/WE when ACT_N is high. Custom Fields values: ['novalue'] Troubleshooting 15012250586 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']