Error: Verilog HDL error at altera_irq_clock_crosser.sv(21): module "altera_irq_clock_crosser" cannot be declared more than once File: <directory path>/altera_irq_clock_crosser.sv Line: 21 - Error: Verilog HDL error at altera_irq_clock_crosser.sv(21): module "altera_irq_clock_crosser" cannot be declared more than once File: <directory path>/altera_irq_clock_crosser.sv Line: 21 Description Due to a problem in the Quartus® II software version 12.1, you may see this error during generation of Qsys systems that utilize IRQ Clock Crosser Logic. Resolution To workaround this problem follow the steps below: Open the altera_irq_clock_crosser_hw.tcl file located in the Quartus II installation directory in a text editor: <Quartus II install directory>\ip\altera\merlin\altera_irq_clock_crosser Remove the line: "set_module_property SIMULATION_MODEL_IN_VERILOG true" Add the line: "add_file altera_irq_clock_crosser.sv {SYNTHESIS SIMULATION}" Save the file and re-generate the Qsys system This problem is fixed for the Quartus II software version 13.0 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']