Why do I get minimum period timing violation in UniPHY-based DDR3 SDRAM Controller on a Stratix® V device? - Why do I get minimum period timing violation in UniPHY-based DDR3 SDRAM Controller on a Stratix® V device? Description You might see minimum period violations on address or command data-path in the Quartus® II software version 11.1SP2 and earlier if the UniPHY-based DDR3 SDRAM memory interface design in a Stratix® V device is combined with user logic that has packed registers in the periphery. Resolution This problem is fixed starting with the Quartus® II software version 12.0. Custom Fields values: ['novalue'] Troubleshooting 1408021257 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.1.2 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']