XIP2201B: ASCON, A Lightweight Cryptographic Suite for AEAD and Hashing, balanced (XIP22 - Ascon IP core implements a lightweight, sponge-based encryption algorithm, being ideal for constrained environments such as IoT devices. Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Ascon IP core implements a lightweight, sponge-based encryption algorithm, being ideal for constrained environments such as IoT devices. Ascon performs three cryptographic primitives: Authenticated Encryption with Associated Data (AEAD), hashing, and extendable output function (XOF), offering a smaller alternative for e.g. AES-GCM and SHA-3 IP cores. Networking / Security Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP2201B: ASCON, A Lightweight Cryptographic Suite for AEAD and Hashing, balanced (XIP22 Key Features Small Resource Requirements: XIP2201B requires only approximately 2100 Logic Elements (LEs) on a typical FPGA implementation and can still provide over 2 Gbps throughput. Offering Brief Yes No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049UQzMAM What's Included Encrypted RTL or source code Ordering Information XIP2201B: a1JUi0000049UQzMAM Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2026-04-21T12:58:33.000+0000 Ascon IP core implements a lightweight, sponge-based encryption algorithm, being ideal for constrained environments such as IoT devices. Partner Solutions