Why do I have timing violations in a flat compile of my OpenCL BSP? - Why do I have timing violations in a flat compile of my OpenCL BSP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4, you may see a timing violation after a flat compile of your OpenCL BSP. This is caused by a problem with order in which the .sdc (Synopsys Design Constraints) file is read. Resolution A patch is available to workaround this problem for the Intel® Quartus® Prime Pro Edition software version 20.4. Download and install Patch 0.32pro from the appropriate link below. Download patch Intel® Quartus® Prime Pro Edition 20.4 Patch 0.32pro for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 20.4 Patch 0.32pro for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 20.4 Patch 0.32pro (.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 21.1 Custom Fields values: ['novalue'] Troubleshooting 1308552680 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']