RapidIO II IP Core Does Not Set RESPONSE_VALID in Port 0 Link Maintenance Response CSR After Transmitting link-request reset-device Control Symbol - RapidIO II IP Core Does Not Set RESPONSE_VALID in Port 0 Link Maintenance Response CSR After Transmitting link-request reset-device Control Symbol Description After the RapidIO II IP core sends a link-request reset-device control symbol on the RapidIO link, it should set the RESPONSE_VALID bit in the Port 0 Link Maintenance Response CSR (offset 0x144). However, the IP core does not set the register bit in this case. Resolution This issue has no workaround. This issue will be fixed in a future version of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']