Why does the Serial Digital Interface (SDI) II MegaCores rx_pll_locked signal occasionally toggle? - Why does the Serial Digital Interface (SDI) II MegaCores rx_pll_locked signal occasionally toggle? Description For HD-SDI and 3G-SDI video standards, the CDR mode of the transceiver is lock to data (LTD) mode. Hence the rx_pll_locked signal of Serial Digital Interface (SDI) II MegaCore® may oscillate when the transceiver is correctly locked to the incoming data in HD-SDI or 3G-SDI standard. However, for SD-SDI video standard, the CDR mode is lock to reference clock (LTR) mode, the rx_pll_locked signal of SDI II MegaCore remain locked at all times. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']