Using the GTS Ethernet Hard IP - 22 Minutes Are you beginning a new Agilex™ 5 or Agilex™ 3 FPGA design that uses an Ethernet interface? If so, the Using the GTS Ethernet Altera® FPGA Hard IP course is a good place to start. After reviewing the GTS transceiver architecture, this course will walk you through the transceiver block when configured for 10G or 25G Ethernet. It will then introduce you to the IP that you will need to complete your design. Finally, the course will provide some important guidelines that will help with your design’s success. Course Objectives At course completion, you will be able to: Customize the GTS Ethernet Hard IP Build an FPGA design using GTS Ethernet Hard IP Skills Required Understanding of the Ethernet protocols, particularly 10G and 25G Ethernet Familiarity with FPGA/CPLD design flow Familiarity with the Quartus® Prime Pro design software Familiarity with Altera® Agilex™ 5 or Agilex™ 3 FPGA transceiver architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com. Reference Course Code: FPGA_OGTSEHIP. FPGA_OGTSEHIP. <p>Using the GTS Ethernet Hard IP</p>