RapidIO 4x 5Gbaud on Intel® Stratix® V GX Family fail recovery timing - RapidIO 4x 5Gbaud on Intel® Stratix® V GX Family fail recovery timing Description Designs using our RapidIO MegaCore running at 5Gbaud in 4x mode and targetting the Stratix® V GX Family will observe recovery timing violations. This is due to the promotion of core reset signals to Global Clock lines. Preventing the promotion of the internal reset signals to Glock Clock lines will resolve the recovery timing failures. This issue will be fixed in the ACDS 12.1 release. Resolution Create a quartus.ini file. In that file, add the following parameter setting. fsv_clocks_min_core_autopromote_fanout=5000 Make sure that the quartus.ini file resides in your project directory. Custom Fields values: ['novalue'] Troubleshooting 44190 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']