Arria 10 HPS - DMA EMAC reset issue - Arria 10 HPS - DMA EMAC reset issue Hello, We are bring-up the custom Arria 10 board, we have some issue with HPS GMAC in U-Boot. Arria 10 connect to SFP (1 G Ethernet) , our interface is : HPS EMAC0 → FPGA GMII-to-SGMII Converter → SFP (SGMII PHY) We are working without MDC/MDIO , in fixed mode. During our testing we performed ping and after this we read register 0xFF801000 and we received value 0x00020101( Last bit DMA_BUS_MODE.SWR = 1 instead of the 0). We checked : The input clock of 125 MHz by oscilloscope - looks ok. Reset Manager: 0xFFD05024 = 0xFF7FBEBE (EMAC0 is released from reset). Bridge is working. GMII-to-SGMII registers are accessible Device tree addresses were verified agaonst the .sopcinfo file Looking forward to your response, thanks in advance. Replies: Re: Arria 10 HPS - DMA EMAC reset issue Thanks for sharing your resolution! Replies: Re: Arria 10 HPS - DMA EMAC reset issue Hello, We found the root cause and resolved the issue. The problem was that the PLL in the FPGA GMII-to-SGMII clock path was not locked. As a result, the required clocks supplied to the HPS EMAC were not valid, and the DMA software reset bit remained asserted: DMA_BUS_MODE.SWR = 1 This behavior matches the Arria 10 documentation: When using the FPGA GMII/MII interface, you must have a stable RX clock (emac_clk_rx_i) and TX clock (emac_clk_tx_i) supplied from the PHY to the EMAC before bringing the EMAC out of reset. The register description for DMA_BUS_MODE.SWR also states that the bit is cleared automatically only after the reset operation has completed in all active GMAC clock domains. Therefore, all PHY input clocks required by the selected interface must be present for the software reset to complete. In our case, the PLL lock condition could not be determined through the available HPS registers. We were only able to identify the issue using Signal Tap. To verify the clock path, the FPGA firmware team implemented a counter driven by the relevant clock. The counter showed that the expected clock was not running, which confirmed that the PLL had not locked. After fixing the PLL configuration and verifying that the clocks were active and stable, the SWR bit cleared successfully and the Ethernet interface started working. Thank you for the guidance. The recommendation to verify emac_clk_rx_i and emac_clk_tx_i using Signal Tap helped us identify the root cause. Replies: Re: Arria 10 HPS - DMA EMAC reset issue Hi LironAvrhmov , How your debug is going, did the previous information helped to root cause the issue? Replies: Re: Arria 10 HPS - DMA EMAC reset issue Please confirm whether the U-Boot initialization sequence is correct. First, make sure the FPGA has entered user mode and that all related soft logic, including the GMII-to-SGMII bridge, PCS, and transceiver path, has been loaded and released from reset. Next, release reset on the PHY/SGMII side so that valid clocks can be generated. Then, confirm that both emac_clk_rx_i and emac_clk_tx_i presented to the HPS EMAC are stable and active. If there is no status register for this, Signal Tap or a simple counter can be used for verification. After that, configure the required System Manager settings, such as phy_intf_sel and fpgaintf_en_3. Finally, release the EMAC from reset and then trigger the Ethernet / DMA initialization. You can try troubleshooting in this order first. BR， Zheng Replies: Re: Arria 10 HPS - DMA EMAC reset issue Hi LironAvrhmov , The software reset triggered by DMA_BUS_MODE.SWR happens in the TX and RX clock domains. DMA_BUS_MODE.SWR will de-assert it self only after the the reset sequence has completed on all GMAC clock domains. A common cause for this issue is that emac_clk_rx_i and emac_clk_tx_i (clocks from external PHY) are not free running at the time of the SWR assertion. Also, as you are using the Fabric interface you need to have all the soft logic out of reset before bringing up the Ethernet interfaces in u-boot, which I think you have as bridges and GMII-to-SGMII registers are accesible. As a general rule, check that your system is fulfilling all the requirements listed in here . To confirm if the clocks from the PHY are ok, you can do a signal tap capture before trying to bring the ethernet interface in u-boot. Let me know if you have any question with the provided information. Regards - Hector