Agilex 5 with DDR4 DIMM fitter crashes - Agilex 5 with DDR4 DIMM fitter crashes Hi, I have instantiated one EMIF for DDR4 DIMM. I cant' get successfull compile because the fitter crashes. Do you have any idea? I have attached the problem report and also the small project to replicate the problem. Regards, Masaru Replies: Re: Agilex 5 with DDR4 DIMM fitter crashes Hi Adzim, OK, I will reference the example design for my start. But it is not handy for me because it was generated by platform designer and have internal bus connection logic blocks my reading. Another topic, exporting axi4 bus does not lead crash, only axi4lite bus does. Thank you very much for your help. Regards, Masaru Replies: Re: Agilex 5 with DDR4 DIMM fitter crashes Hi Masaru, I'm not sure right now why the Quartus got an error when using the Virtual pins for AXI4 signals in EMIF IP interface. I will investigate further in future. For the best option, you can start with the EMIF example design and modify with your own logic. Such as replace the traffic generator with your own logic. Regards, Adzim Replies: Re: Agilex 5 with DDR4 DIMM fitter crashes I got successfull fit. Thank you very much. But in my original design, I put virtual pin assignment to all axi4 and axi4lite pins, and it doesn't consume any pins. Is it illegal? Replies: Re: Agilex 5 with DDR4 DIMM fitter crashes Hi Masaru, I think this error occurred because the axi4 and axi4lite ports are export to top level file. You can try to remove these ports from export to top level file and compile the design again. I recommend generating an example design and start modifying the example design with your own logic. Here is what I mean to not export the axi4 and axi4lite ports. /* agilex 5 test */ module Agilex5Test ( /*output logic s0_axi4_clock_out, // output, width = 1, s0_axi4_clock_out.clk output logic s0_axi4_reset_n, // output, width = 1, s0_axi4_ctrl_ready.reset_n input logic [34:0] s0_axi4_awaddr, // input, width = 35, s0_axi4.awaddr input logic [1:0] s0_axi4_awburst, // input, width = 2, .awburst input logic [6:0] s0_axi4_awid, // input, width = 7, .awid input logic [7:0] s0_axi4_awlen, // input, width = 8, .awlen input logic s0_axi4_awlock, // input, width = 1, .awlock input logic [3:0] s0_axi4_awqos, // input, width = 4, .awqos input logic [2:0] s0_axi4_awsize, // input, width = 3, .awsize input logic s0_axi4_awvalid, // input, width = 1, .awvalid input logic [13:0] s0_axi4_awuser, // input, width = 14, .awuser input logic [2:0] s0_axi4_awprot, // input, width = 3, .awprot output logic s0_axi4_awready, // output, width = 1, .awready input logic [34:0] s0_axi4_araddr, // input, width = 35, .araddr input logic [1:0] s0_axi4_arburst, // input, width = 2, .arburst input logic [6:0] s0_axi4_arid, // input, width = 7, .arid input logic [7:0] s0_axi4_arlen, // input, width = 8, .arlen input logic s0_axi4_arlock, // input, width = 1, .arlock input logic [3:0] s0_axi4_arqos, // input, width = 4, .arqos input logic [2:0] s0_axi4_arsize, // input, width = 3, .arsize input logic s0_axi4_arvalid, // input, width = 1, .arvalid input logic [13:0] s0_axi4_aruser, // input, width = 14, .aruser input logic [2:0] s0_axi4_arprot, // input, width = 3, .arprot output logic s0_axi4_arready, // output, width = 1, .arready input logic [511:0] s0_axi4_wdata, // input, width = 512, .wdata input logic [63:0] s0_axi4_wstrb, // input, width = 64, .wstrb input logic s0_axi4_wlast, // input, width = 1, .wlast input logic s0_axi4_wvalid, // input, width = 1, .wvalid input logic [63:0] s0_axi4_wuser, // input, width = 64, .wuser output logic s0_axi4_wready, // output, width = 1, .wready input logic s0_axi4_bready, // input, width = 1, .bready output logic [6:0] s0_axi4_bid, // output, width = 7, .bid output logic [1:0] s0_axi4_bresp, // output, width = 2, .bresp output logic s0_axi4_bvalid, // output, width = 1, .bvalid input logic s0_axi4_rready, // input, width = 1, .rready output logic [63:0] s0_axi4_ruser, // output, width = 64, .ruser output logic [511:0] s0_axi4_rdata, // output, width = 512, .rdata output logic [6:0] s0_axi4_rid, // output, width = 7, .rid output logic s0_axi4_rlast, // output, width = 1, .rlast output logic [1:0] s0_axi4_rresp, // output, width = 2, .rresp output logic s0_axi4_rvalid, // output, width = 1, .rvalid input logic s0_axi4lite_clock, // input, width = 1, s0_axi4lite_clock.clk input logic s0_axi4lite_reset_n, // input, width = 1, s0_axi4lite_reset_n.reset_n input logic [26:0] s0_axi4lite_awaddr, // input, width = 27, s0_axi4lite.awaddr input logic [2:0] s0_axi4lite_awprot, // input, width = 3, .awprot input logic s0_axi4lite_awvalid, // input, width = 1, .awvalid output logic s0_axi4lite_awready, // output, width = 1, .awready input logic [26:0] s0_axi4lite_araddr, // input, width = 27, .araddr input logic [2:0] s0_axi4lite_arprot, // input, width = 3, .arprot input logic s0_axi4lite_arvalid, // input, width = 1, .arvalid output logic s0_axi4lite_arready, // output, width = 1, .arready input logic [31:0] s0_axi4lite_wdata, // input, width = 32, .wdata input logic [3:0] s0_axi4lite_wstrb, // input, width = 4, .wstrb input logic s0_axi4lite_wvalid, // input, width = 1, .wvalid output logic s0_axi4lite_wready, // output, width = 1, .wready input logic s0_axi4lite_bready, // input, width = 1, .bready output logic [1:0] s0_axi4lite_bresp, // output, width = 2, .bresp output logic s0_axi4lite_bvalid, // output, width = 1, .bvalid input logic s0_axi4lite_rready, // input, width = 1, .rready output logic [31:0] s0_axi4lite_rdata, // output, width = 32, .rdata output logic [1:0] s0_axi4lite_rresp, // output, width = 2, .rresp output logic s0_axi4lite_rvalid, // output, width = 1, .rvalid */output logic [1:0] mem_0_cke, // output, width = 2, mem_0.mem_cke output logic [1:0] mem_0_odt, // output, width = 2, .mem_odt output logic [1:0] mem_0_cs_n, // output, width = 2, .mem_cs_n output logic [16:0] mem_0_a, // output, width = 17, .mem_a output logic [1:0] mem_0_ba, // output, width = 2, .mem_ba output logic [1:0] mem_0_bg, // output, width = 2, .mem_bg output logic mem_0_act_n, // output, width = 1, .mem_act_n output logic mem_0_par, // output, width = 1, .mem_par inout logic [63:0] mem_0_dq, // inout, width = 64, .mem_dq inout logic [7:0] mem_0_dqs_t, // inout, width = 8, .mem_dqs_t inout logic [7:0] mem_0_dqs_c, // inout, width = 8, .mem_dqs_c input logic mem_0_alert_n, // input, width = 1, .mem_alert_n output logic [1:0] mem_0_ck_t, // output, width = 2, mem_ck_0.mem_ck_t output logic [1:0] mem_0_ck_c, // output, width = 2, .mem_ck_c output logic mem_0_reset_n, // output, width = 1, mem_reset_n.mem_reset_n input logic oct_rzqin_0, // input, width = 1, oct_0.oct_rzqin input logic ref_clk // input, width = 1, ref_clk.clk ); - 2024-12-12