Why does the F-Tile PMA/FEC Direct PHY Intel® FPGA IP with PMA type set FGT, Enable RS-FEC disabled, Datapath clocking mode set PMA, PMA width set 32 and Enable TX FGT PLL fractional mode enabled fail to pass Quartus Support Logic Generation? - Why does the F-Tile PMA/FEC Direct PHY Intel® FPGA IP with PMA type set FGT, Enable RS-FEC disabled, Datapath clocking mode set PMA, PMA width set 32 and Enable TX FGT PLL fractional mode enabled fail to pass Quartus Support Logic Generation? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile PMA/FEC Direct PHY IP variant with the “ PMA type ” parameter set to “ FGT ”, the “ Enable RS-FEC ” parameter disabled , the “ Datapath clocking mode ” set to “ PMA ”, the “ PMA width ” parameter set to “ 32 ”, and the “ Enable TX FGT PLL fractional mode ” parameter enabled will fail to pass Quartus Support Logic Generation. The errors that are generated will contain a string that is similar to the one shown below: Error (21843): user.bb_f_ux_tx[0] -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx Error (21843): is_used == TRUE Error (21843): location == UX15 Error (21843): synth_lc_slow_f_out_hz == 8000000000 Error (21843): synth_lc_slow_f_ref_hz == 182000000 Error (21843): synth_lc_slow_f_rx_postdiv_hz == 320000000 Error (21843): synth_lc_slow_f_vco_hz == 8000000000 Error (21843): synth_lc_slow_rx_postdiv_counter == 50 Error (21843): tx_tuning_hint == TX_TUNING_HINT_DISABLED Resolution To work around this problem, you must add a QSF assignment to your project that overrides the setting for the “ synth_lc_slow_rx_post_counter. ” Below is an example of the required assignment. Note that the hierarchy will be specific to your design. set_instance_assignment -name HSSI_PARAMETER "synth_lc_slow_rx_postdiv_counter=25" -to u0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx This problem was fixed in version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16025463193 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']