Why does my fractional PLL with the reconfiguration feature enabled fail to lock in Stratix V devices? - Why does my fractional PLL with the reconfiguration feature enabled fail to lock in Stratix V devices? Description Due to a problem in Quartus® II versions 11.1SP2 and earlier, fractional PLLs implemented with the Altera® PLL IP and attached Altera PLL reconfig IP may fail to lock when implemented in certain locations on Stratix® V devices. An additional symptom is that the mgmt_waitrequest signal is always asserted. Resolution If PLLs with reconfiguration are used on Stratix V devices, use version 12.0 or later of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.0 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']